As mobile phones, portable media players, personal digital assistants, and other mobile devices have proliferated, manufacturers have continually improved the features that are offered to device users. Offering additional features has typically required manufacturers to increase the processing power of devices. In current mobile devices, for example, it is not uncommon for the device to contain multiple computer processors or other processing elements. For example, mobile phones often contain a baseband processor, a media processor, and an LCD controller. Each of the processing components in a mobile device may access various memory areas in which an operating system or other applications are stored. The processing components may communicate with the memory and with other components at different communication rates and using different communication protocols.
As mobile devices have continued to shrink in size, manufacturers have needed to optimize the device architectures in order to minimize the number of components that are contained within a device. Size reductions are often achieved by combining the functionality from many semiconductor components into a single semiconductor component. When manufacturers sought to reduce the number of components that are contained within a mobile device, however, several problems arose that were particularly acute in a multi-processor environment. First, having several processing components communicating with a single memory component required a mechanism to ensure that all components would have access to the memory device. Such a challenge has been mitigated by the introduction of multi-port memory devices, such as the multi-port device disclosed in U.S. patent application Ser. No. 10/045,297, entitled “Communications Architecture for Memory-Based Devices”, filed Nov. 7, 2001, and incorporated herein in its entirety by this reference. A multi-port memory architecture allows accessing components to communicate with a common shared memory through dedicated ports. Second, the various processing components in a mobile device may communicate with each other and with memory devices at different data rates. When using numerous components, manufacturers were able to select a memory device having a speed that matched the requirements of the processing component to which it was connected. By reducing the component count, however, an incompatibility can arise between transmission and reception communication speeds of processing components and memory devices. It would therefore be advantageous to develop a multi-port memory device that is suitable for communicating with a wide variety of processing components at various data communication speeds.